1. Field of the Invention
This invention relates, in general, to counters and more particularly to ripple counters having a reduced propagation delay.
2. Background Art
Known ripple counters having "D" type flip-flops comprise a first flip-flop having a clock input responsive to a clock pulse, and a D input responsive to a Q output. A clock input of a second flip-flop is responsive to a Q output of the first flip-flop, and a D input of the second flip-flop is responsive to a Q output of the second flip-flop. A Q output of the second flip-flop may clock a third flip-flop in a similar manner, with the number of flip-flops so connected determined by the desired count length, or divider ratio. Each flip-flop serially connected in this manner introduces a propagation delay between the first clock input and the last Q output. This propagation delay can be reduced by operating the flip-flops at higher bias currents.
Circuitry requiring low currents, such as the Electronic Telephone Chip (ETC) which includes a Dual Tone Multifrequency (DTMF) Generator For Touch Tone Dialing, may require that the current for each gate be limited. I.sup.2 L technology used in such circuitry has speed limitations, such that more current is needed for lower propagation delays. When a ripple counter as described above is used to implement a programmable counter, the propagation delay of the flip-flops becomes the limiting factor in determining the highest clock frequency.
Therefore, what is needed is a flip-flop circuit having reduced propagation delay and a reduced total current requirement.